1. Field of the Invention
The present invention relates to a semiconductor memory device having a defect repairing redundant circuit.
2. Related Background Art
As shown in FIG. 20, a typical dynamic random access memory (DRAM) comprises a memory array 51, a row decoder 61, a column decoder 71 and an I/O control circuit 75. The memory array 51 has a plurality of memory cells 53 arranged as a matrix, a plurality of word lines 55 and a plurality of bit lines 57. Each of the memory cells 53 generally comprises a MOS transistor 53a and a capacitor 53b. The gate of the transistor 53a is connected to one of the word lines 55. One of the source and drain of the transistor 53a is connected to one of the bit lines 57, and the other is connected to one of the electrodes of the capacitor 53b in the same memory cell. Furthermore, the other electrode of the capacitor 53b is connected to a power supply line having a predetermined potential. In addition, the gate of at least one transistor 53a is connected to each of the word lines 55, and one of the source and drain of at least one transistor 53a is connected to each of the bit lines 57.
In the DRAM with such a construction, when a row address and a column address are inputted from the outside, the row decoder 61 selects a word line 55 or a predetermined number of word lines 55 on the basis of the row address to activate the selected word lines 55, and the column decoder 71 selects a column selection line 73 or a predetermined number of column selection lines 73 on the basis of the column address to activate the selected column selection lines 73. Since a pair of bit lines or pairs of bit lines are connected to one of the column selection lines 73 via a column switch, the pair or pairs of bit lines connected to the activated column selection lines 73 are activated. Thus, data are read out of the corresponding memory cell or data are written in the corresponding memory cell by means of the I/O control circuit 75.
Large-scale semiconductor memory device, such as DRAMs, have a defect repairing redundant circuit in order to enhance the yield of products. The redundant circuit has spare elements arranged for a plurality of elements in a memory array. Furthermore, throughout the specification, the term "element" means a row element (a word line or a bundle of a predetermined number of word lines) or a column element (a pair of bit lines or a bundle of a predetermined number of bit lines, or a column selection line or a bundle of a predetermined number of column selection lines). The term "spare element", which will be described later, means the same.
A typical DRAM memory array determines how many elements are simultaneously activated in the whole array, in view of electric power consumption, the number of data outputs in the whole chip and so forth. In addition, the DRAM memory array are divided into a plurality of blocks so that only one element is simultaneously activated in one of the blocks. The redundant circuit predicts the defect distribution in the whole array and determines a number of spare element groups necessary to a block of a specific capacity. That is, a repair region of a specific capacity (area), in which the spare element groups can freely repair defects, is determined. Each of the spare element groups has a plurality of spare memory cells, and a plurality of spare elements, each of which selects a predetermined number of spare memory cells. Similar to the memory cell, each of the spare memory cells comprises a MOS transistor and a capacitor.
FIG. 21 shows an example of the arrangement of a redundant circuit of a conventional DRAM memory array 1. In this example, the memory array 1 is divided into two memory blocks 1a and 1b which sandwich a sense amplifier 2 therebetween. Spare element groups 3a and 3b, each of which has n spare elements, are arranged so as to belong to the respective memory blocks 1a and 1b in order to replace defective elements of a plurality of elements 5a and 5b in the respective blocks 1a and 1b. That is, a range in which defects are repaired by the spare element group 3a corresponds to the memory block 1a. This memory block 1a is a repair region corresponding to the spare element group 3a. Similarly, the memory block 1b is a repair region corresponding to the spare element group 3b.
In a case where each of the elements 5a and 5b is a row element (i.e., a word line or a bundle of word lines), a pair of bit lines in the respective blocks 1a and 1b are designed to be connected to all of the word lines and the spare word lines in the spare element groups 3a and 3b via the gates of cell transistors, the drains (or sources) of which are connected to the pair of bit line. Therefore, when a plurality of word lines are simultaneously activated in the respective blocks 1a and 1b , data transmitted from a plurality of memory cells collide on the bit line. For that reason, the number of the word lines simultaneously activated in each of the blocks 1a and 1b (i.e., each of the repair regions) is only one, and the number of defective word lines capable of being simultaneously replaced is also only one. For the same reason, the number of the spare word lines simultaneously activated in each of the spare element groups 3a and 3b corresponding to each of the blocks 1a and 1b is also only one.
In a case where the elements 5a and 5b are column elements (i.e., column selection lines), each of the spare element groups 3a and 3b has n spare column selection lines. In addition, each of the blocks 1a and 1b serving as a repair region corresponding to each of the spare element groups 3a and 3b has a plurality of column selection lines which are connected to data lines via the gates of column switches (transistors), the drains (or sources) of which are connected to the same data line or the same pair of data lines. The spare column lines forming the spare elements are also connected to the same data line. Also in this case, the number of the column selection lines capable of being simultaneously activated in each of the blocks 1a and 1b is only one, and the number of the defective column selection lines capable of being simultaneously replaced is also only one. For the same reason, the number of the spare column selection lines capable of being simultaneously activated in each of the spare element groups 3a and 3b corresponding to each of the blocks 1a and 1b is also only one.
FIG. 22 shows an another example of the arrangement of a redundant circuit of a conventional DRAM memory array 1. In this example, the memory array 1 is arranged as a redundant array including spare element groups 3a and 3b which have word and bit lines independent of memory blocks 1a and 1b. Also in this case, the number of elements simultaneously activated for each of the blocks 1a and 1b is only one, and each of the blocks 1a and 1b serves as a repair region wherein defects are repaired by each of the spare element groups 3a and 3b.
In this example, the memory array is divided into two parts so that the number of elements simultaneously activated in each of the blocks 1a and 1b is only one when two elements are simultaneously activated in the whole memory array, and each of the blocks 1a and 1b serves as a repair region. In addition, the spare element groups 3a and 3b for the respective blocks 1a and 1b are formed as separate arrays having bit and data lines independent of those of the memory blocks 1a and 1b, and all of the spare element groups 3a and 3b are connected to the same bit line and data line via the gate of a cell transistor or the gate of a column switch. Also in this case, the number of spare elements simultaneously activated in a redundant array formed by the spare element groups 3a and 3b is only one. Therefore, the number of defective elements capable of being simultaneously replaced in the whole memory array (1a, 1b) is only one.
In the conventional examples shown in FIGS. 21 and 22, the number x of elements simultaneously activated by the same address is 2. In addition, a ratio y (=S.sub.1 /S.sub.2) of a memory capacity (area) S.sub.1 of a region (i.e., block 1a or 1b) of a memory array 1 per one of two elements simultaneously activated to a memory capacity (area) S.sub.2 of a repair region (block 1a or 1b) repaired by a spare element group is 1. The number of elements simultaneously activated in a repair region is also 1 maximum.
In order to replace defective elements by the above described spare element groups 3a and 3b, a total of n redundant control circuits RCTRL.sub.1, . . . RCTRL.sub.n corresponding to the respective spare element groups 3a and 3b, each of which includes n spare elements, are used as shown in FIG. 23. Each of the redundant control circuits RCTRL.sub.1, . . . RCTRL.sub.n stores a defective address found by a test at the stage of a wafer, and controls the replacement of a defective element with a spare element when the defective address is inputted. Each of the redundant control circuits RCTRL.sub.1, . . . RCTRL.sub.n includes a fuse serving as a defective address storage circuit, a fuse latch circuit, a fuse circuit, a fuse decoding circuit, a comparing circuit and so forth. When an address is inputted, n redundant control circuits RCTRL.sub.1, . . . RCTRL.sub.n are activated with respect to each of x elements (x=2 in the examples shown in FIGS. 21 and 22) simultaneously activated, and it is detected whether the input address is coincident with an address programmed in each of the redundant control circuits RCTRL.sub.i by blowing the fuse.
When the input address is different from an address programmed in a certain redundant control circuit RCTRL.sub.i (i=1, . . . n), a signal ON.sub.i is outputted from the redundant control circuit RCTRL.sub.i. When all of n redundant control circuits RCTRL.sub.i (i=1, . . . n) output the signals ONi, a mismatch is detected by a NAND gate G1, and a repair region activating signal ENABLE is generated from an inverter G2. Thus, the replacement of elements is not carried out, and one element determined by the input address is activated in each of the repair regions.
When an address programmed in a certain redundant control circuit RCTRL.sub.i is inputted, the redundant control circuit RCTRL.sub.i does not output the signal ON.sub.i, and outputs a spare element activating signal REN.sub.i. By this spare element activating signal REN.sub.i, the defective element is replaced with a spare element.
In either redundant circuit systems shown in FIGS. 21 and 22, since one element is simultaneously activated in the blocks 1a and 1b serving as the respective repair regions of the spare element groups 3a and 3b, it is required to detect the coincidence of the input address with the defective address and to control the replacement, i.e., to activate the n redundant control circuits RCTRL.sub.1, . . . RCTRL.sub.n shown in FIG. 23, for both of the spare element groups 3a and 3b when the address is inputted. More specifically, in the redundant circuit control system of the conventional DRAM, n redundant control circuits are simultaneously activated for each of x elements simultaneous activated (i.e., n.multidot.x redundant control circuits are simultaneously activated in the whole memory array) when an address is inputted. Therefore, there is a problem in that the total of redundant control circuits has great electric current consumption.